Integrated circuits are widely used in consumer and commercial applications. As the integration density of integrated circuit devices continues to increase, topography differences on the integrated circuit may continue to increase. These topography differences between regions of high and low topography may make it increasingly difficult to form high density interconnections, also referred to as wiring layers, on integrated circuits. As used herein, the terms "high" and "low" are used to define topography differences relative to one another, without indicating absolute topography levels.
In particular, in integrated circuit memory devices, the region of high topography generally includes a memory cell array region, while the region of low topography generally includes a peripheral circuit region in which circuits that are used to support the memory cell array are fabricated. More specifically, in a Dynamic Random Access Memory (DRAM) integrated circuit, the region of high topography generally includes a DRAM cell array region that includes a plurality of capacitors therein, and the region of low topography includes a DRAM peripheral circuit region. In DRAM devices that include stacked capacitors, topography differences of up to 1 .mu.m or more may be present.
Finally, it is also known to provide Merged Memory and Logic (MML) integrated circuits that merge the functions of memory integrated circuits and logic integrated circuits into a single integrated circuit substrate. In these MML integrated circuits, the region of high topography generally includes a memory cell array region and the region of low topography generally includes a logic circuit region. Particularly for Merged DRAM and Logic (MDL) integrated circuits, topography differences of up to 1 .mu.m or more may be present, due to the use of stacked capacitors or other three-dimensional capacitor structures in the memory array region.
FIGS. 1-3 are cross-sectional views illustrating the fabrication of conventional DRAM devices in order to illustrate how these large topography differences can arise. FIGS. 1-3 illustrate a DRAM fabrication process in which a Capacitor-On-Bitline (COB) structure is utilized. In FIGS. 1-3, reference letter A indicates a region of high topography, specifically the DRAM cell array region, and reference letter B indicates a region of low topography, specifically a DRAM peripheral circuit region.
Referring now to FIG. 1, a field oxide layer 12 is formed in an element-isolation zone of an integrated circuit substrate such as a semiconductor substrate 10, so that the active zone where an active element is formed thereon is defined. A gate insulating layer is formed in the active zone of the substrate 10, and gate electrodes 14 are formed on predetermined parts of the gate insulating layer and the field oxide layer 12, respectively.
Next, the substrate 10 is ion-implanted by a low concentration of dopants. Thereafter, spacers 16 comprising insulating material are formed on both sidewalls of the gate electrode 14. The substrate 10 is ion-implanted by dopants of high concentration, to form source/drain regions having a Lightly Doped Drain (LDD) structure in the substrate 10 where both edges of the gate electrode 14 are positioned. As a result, a Field Effect Transistor (FET) is formed.
A buffer oxide layer 18 is formed on the substrate 10 including on the gate electrodes 14 and on the field oxide layer 12. A first insulating layer 20 comprising a high-temperature oxide film-type material, such as Boron Phosphorus Silicate Glass (BPSG), is formed on the surface resulting from the above process, and the first insulating layer 20 is allowed to reflow at a predetermined temperature. The formation of the buffer oxide layer 18 can prevent the transistor from being damaged by doping of P-ions or B-ions into the gate electrode 14, which may occur when the first insulating layer 20 is formed with a high-temperature oxide film-type material such as BPSG, or from being damaged by plasma, which can occur when the film is formed by evaporation.
First direct contact holes are formed by selectively etching a predetermined part of the first insulating layer 20 so that the surface of the substrate 10 on which bit lines will be formed is exposed. A conductive film is formed on the first insulating layer 20 including in the first contact hole, also referred to as a Direct Contact (DC) hole. Bit line 22 is formed by selectively etching so that the surface of the insulating layer 20 is partly exposed.
As shown in FIG. 2, a second insulating layer 24 comprising a high-temperature oxide film-type material (for example BPSG) is formed on the first insulating layer 20 including on the bit line 22. The second insulating layer 24 is allowed to reflow at a predetermined temperature. Second contact holes, also referred to as Buried Contact (BC) holes, are formed by selectively etching predetermined parts of the second insulating layer 24, the first insulating layer 20 and the buffer oxide layer 18 so that the surface of the substrate 10, wherein a capacitor will be formed, is partly exposed. A conductive layer comprising polysilicon including dopants of high concentration, is formed on the second insulating layer 24 including in the second buried contact hole. A storage electrode 26 is formed on the high topography region A by selectively etching the conductive layer. A dielectric layer 28 is formed on the surface of the storage electrode 26. A conductive layer comprising polysilicon including dopants of high concentration is formed on the second insulating layer 24 including on the dielectric layer 28. A plate electrode 30 is formed by selectively etching the conductive layer. As a result, a stacked capacitor structure including the storage electrode 26, the dielectric layer 28 and the plate electrode 30 is formed in the high topography memory cell array region A.
A third insulating layer 32 comprising high temperature oxide film-type material (for example BPSG) is formed on the second insulating layer 24 including on the capacitor. The third insulating layer is allowed to reflow at a predetermined temperature. Thereafter, third contact holes having various aspect ratios are formed by etching in order the first, second and third insulating layers 20, 24, 32, the buffer oxide layer 18 and the gate insulating layer, so that the surface of the plate electrode 30 in the low topography peripheral circuit region B and the surface in the active region are partly exposed.
A glue metal layer having a structure such as "Ti/TiN", a conductive layer comprising Al-based alloy and an anti-reflection layer comprising TiN are formed on the third insulating layer 32 including in the third contact hole. Thereafter, a first metal wiring layer 34 is formed on the high topography memory cell array region A and the low topography peripheral circuit region B, by etching predetermined portions of the layer.
Referring now to FIG. 3, a fourth insulating layer 36 such as "Undoped Silicon Glass (USG)/Silicon-on-Glass (SOG)" is formed on the third insulating layer 32 including on the first metal wire 34. The fourth insulating layer 36 is planarized by using an SOG etch-back process. Via holes are formed in the fourth insulating layer 36 by selectively etching the fourth insulating layer 36 so that the surface of the first wiring layer 34 formed in the peripheral circuit region B is partly exposed.
A glue metal layer having a structure such as "Ti/TiN", a conductive layer comprising Al-based alloy and an anti-reflection layer comprising TiN are formed on the fourth insulating layer 36 including in the via holes. Thereafter, a second wiring layer 38 is formed on the high topography memory cell array region A and on the low topography peripheral circuit region B, by etching predetermined portions of the second wiring layer, to complete the process.
As shown in FIG. 2, for a conventional DRAM device, the first metal wiring layer 34 is formed by forming a conductive film and then etching, while the topography difference between the memory cell array region A and the peripheral circuit region B may be up to 1.0 .mu.m or more due to the capacitor formed in the memory cell region A. This topography difference may create fabrication problems.
In particular, in a conventional DRAM device with a topography difference of 1.0 .mu.m or more, it may be difficult to find a photolithography margin that can be applied to both the high topography memory cell array region A and the low topography peripheral circuit region B. For this reason, the design rule may need to be set so that pitch of the first metal wiring layer 34 has enough margin for the formation of the desired metal pattern.
However, if the design rule is set so that the pitch of the first metal wiring layer 34 has enough margin when the DRAM device is designed, the first metal wiring layer pitch in the peripheral circuit region may need to be set to a similar level. This may produce low gate density in the peripheral circuit region. For example, in an MML/MDL integrated circuit, gate density in the logic region may not be comparable to a pure logic integrated circuit. Thus, MML/MDL integrated circuits with high performance may be difficult to fabricate.